In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as, dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, and NAND, conductive materials are used in the formation of storage cell capacitors as well as in interconnection structures and conductive lines. Thus, formation of conductive materials is an important fabrication process in integrated circuit (IC) production.
The requirements of forming the conductive material may be demanding, since conductive films need to be deposited at reasonably low temperatures tolerated by other materials used in the integrated circuits. In addition, high quality conformal films of the conductive material are often used to cover a highly varied topography on the integrated circuits for forming various conductive structures, such as openings, deep trenches, and container capacitor openings. Furthermore, such films need to be formed with high throughput.
For example, conventional storage cells include two conductive electrodes and a dielectric material interposed therebetween, and are often referred to as “metal-insulator-metal” (MIM) storage cell capacitors. One or more layers of various conductive materials may be used in forming the conductive electrodes. As capacitors decrease in size, the thickness of the dielectric material must be decreased to increase gate capacitance. Decreasing the thickness of conventional dielectric materials, such as silicon dioxide, may result in increased leakage current and reduced reliability of the device. Utilizing a high dielectric constant material between the two conductive electrodes enables increased gate capacitance without the concomitant leakage effects. The use of conductive materials such as platinum, rhodium, iridium, osmium, and alloys thereof, has been proposed for such MIM storage cell capacitors.
Many storage cell capacitors are fabricated which include electrode layers that are formed of a conductive material within a small, high aspect ratio opening. The term “aspect ratio” relates to the depth or height of a structure of an integrated circuit in relation to its width. Most often, platinum is used as the conductive material because platinum a high work function metal that generally reduces leakage in the cell. However, the lack of a practical etching process to remove platinum poses problems during capacitor fabrication. Conventional techniques used to form a platinum electrode include depositing the platinum, followed by CMP (chemical-mechanical polishing) or ion milling to remove extraneous portions of the platinum. However, these techniques may results in undesirable defects in the platinum electrode.
Referring to FIGS. 1A-1C, a conventional method of forming a semiconductor structure 100 including a container-type cell capacitor on a substrate 102 is illustrated. As shown in FIG. 1A, a substrate 102 may include a contact 104 formed therein and may, optionally, be in electrical contact with an underlying interconnect structure (not shown). A dielectric material 106 may be formed over the contact 104 and the substrate 102 and may be formed from materials such as, for example, silicon dioxide (SiO2). A mask material 108 is formed over and in contact with the dielectric material 106 and is patterned to form an aperture (not shown) exposing a region of the dielectric material 106 where it is desired to form a capacitor structure. An opening 110 may be formed using an etching process that selectively removes the dielectric material 106 with respect to the mask material 108.
Thereafter, as shown in FIG. 1B, a conductive material 112 to be used for forming a bottom electrode of the cell capacitor is formed within the opening 110 and on the upper surface of the dielectric material 106. An oxide material 114 may then be applied over the semiconductor structure 100. The oxide material 114 and horizontal portions of the conductive material 112 overlying the dielectric material 106 may then be planarized or etched to form a bottom electrode 116. Ideally, an upper surface of the bottom electrode 116 is coplanar with an upper surface of the dielectric material 106.
However, during planarization, the conductive material 112 may be pushed into the center of the opening 110, resulting in deformation 118 as shown in FIG. 1C. The deformation 118 in the conductive material 112 produces an undesirable profile, which interferes with the formation of additional materials on the semiconductor structure 100. A further problem occurs where the conductive material 112 is exposed to an etching process to form the bottom electrode 116. During the etch, photoresist material 120 is formed over the conductive material 112 and patterned to expose regions of the conductive material 112 to be etched. Upon etching the conductive material 112 back to the dielectric material 106, the photoresist layer 120 may pull back away from the conductive material 112, causing surface regions 122 of the conductive material 112 to be undesirably etched.
To achieve higher-density memory arrays, methods for forming conductive materials and structures suitable for fabricating complex devices with the required enhanced density and reliability to meet future demands are needed.